1. Field of the Invention
The present invention relates to a decoder circuit, more particularly, to a decoder circuit used as a peripheral circuit of a semiconductor memory device e.g., a metal-oxide semiconductor (MOS) type static random access memory (RAM) (MOS-static RAM), which can operate on greatly reduced power consumption when in a non-selected condition.
2. Description of the Prior Art
Recently, semiconductor memory devices, for example MOS-static RAM's, have been produced with a greater bulk storage capacity and higher degree of integration. However, this greater bulk storage capacity and higher degree of integration causes a corresponding increase in the power consumption per one memory chip. The increased power consumption by the memory chips brings about a greater radiation of heat, i.e., a higher calorific value, so that a large-scale cooling means becomes necessary for cooling the memory chips effectively. Moreover, the larger the number of memory chips used in the mass storage semiconductor memory device, the greater the power consumption and the higher the calorific value.
Consequently, problems occur in that the conventional decoder circuit used as one of the peripheral circuits of the semiconductor memory device cannot reduce the power consumption of the semiconductor memory device because a large, wasteful current flows to the decoder circuits in a non-selected condition and less current flows to the decoder circuit in a selected condition.